This invention relates generally to digital integrated circuits for use in data processing computing systems and more particularly, it relates to an asynchronous interrupt status bit circuit which allows no interrupt signals to be missed and prevents a single interrupting signal from being read twice by a host microprocessor.
As is generally known in the microprocessor art, a host microprocessor has the capability of responding to an interrupt input or status signal via an interrupt controller, which operates, upon receipt of a signal, to cause the microprocessor to respond to particular preprogrammed routines under the control of an interrupt program. Most interrupt signals are not due to error conditions but will be part of the normal operation of the system. These interrupt routines are important for many reasons, such as for servicing memory management access violations, input/output devices, and the system clock. For example, such an interrupt signal from an integral timer is used to periodically interrupt the microprocessor so as to keep track of the time. In the event of the receipt of such an interrupt, the interrupt controller sends an interrupt to the microprocessor which causes the microprocessor to send out a read signal to determine what type of interrupt has been requested. The read signal permits the microprocessor to read related interrupt status registers which generate output signals to the microprocessor.
Since interrupt or status signals are asynchronous, which means that they can occur at any time in relationship to the read signal, there has been encountered problems heretofore when the asynchronous interrupt signal and the read signal happen at substantially the same time. In particular, the interrupt signal could be not read or missed, or the interrupt signal could be read twice for a single interrupting condition depending upon if the read signal occurs slightly before or slightly after the interrupt signal. Accordingly, it would therefore be desirable to provide an asynchronous interrupt status bit circuit which guarantees that no interrupting conditions are missed and that no single interrupting condition is indicated twice.